A novel, efficient CNTFET Galois design as a basic ternary-valued logic field
Author(s) -
Peiman Keshavarzian,
Mahla Mohammad Mirzaee
Publication year - 2012
Publication title -
nanotechnology science and applications
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 1.051
H-Index - 28
ISSN - 1177-8903
DOI - 10.2147/nsa.s27550
Subject(s) - carbon nanotube field effect transistor , ternary operation , galois theory , power–delay product , logic family , logic gate , arithmetic , logic synthesis , electronic engineering , field (mathematics) , computer science , mathematics , transistor , electrical engineering , field effect transistor , algorithm , cmos , engineering , discrete mathematics , adder , pure mathematics , voltage , programming language
This paper presents arithmetic operations, including addition and multiplication, in the ternary Galois field through carbon nanotube field-effect transistors (CNTFETs). Ternary logics have received considerable attention among all the multiple-valued logics. Multiple-valued logics are an alternative to common-practice binary logic, which mostly has been expanded from ternary (three-valued) logic. CNTFETs are used to improve Galois field circuit performance. In this study, a novel design technique for ternary logic gates based on CNTFETs was used to design novel, efficient Galois field circuits that will be compared with the existing resistive-load CNTFET circuit designs. In this paper, by using carbon nanotube technology and avoiding the use of resistors, we will reduce power consumption and delay, and will also achieve a better product. Simulation results using HSPICE illustrate substantial improvement in speed and power consumption.
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