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Abstract : The absence of a band-gap and the lack of an adequate synthesis method of high quality graphene on silicon substrates have held back the applications of graphene in electronics and integrated micro- and nano-systems. This research pioneers a novel approach to the synthesis of high-quality and highly uniform few-layer graphene on silicon wafers, based on solid source growth from hetero-epitaxial SiC films. Using a Ni/Cu catalytic alloy high-quality, uniform bilayer graphene directly was realized on silicon wafers, at temperatures compatible with conventional semiconductor processing. The highest ever reported doping for graphene (approx. 1015/cm2), which also corresponded to record low sheet resistance was observed using this process. The p-type metal sheet is grown in-situ on silicon substrates, with processes fully compatible with semiconductor industry and its conduction is unmatched by any classical metal of only 1 nm thickness. This densely intercalated graphene bilayer offers both electrical and mechanical (adhesion) reliability, largely overlooked so far but both essential to qualify for any use in nanodevices. The extremely high doping may open a new area of basic physics investigation. The research illustrates how exceptional properties of the catalytic graphene on silicon substrates can advance a wide spectrum of practical applications ranging from efficient metal replacement at the nanoscale for MEMS/NEMS to miniaturized devices for on-chip energy storage.

Understanding the Fundamental Properties of Transfer-Free, Wafer-Level Graphene on Silicon and its Potential for Micro- and Nanodevices