Open AccessWord Level Predicate Abstraction and Refinement for Verifying RTL Verilog
Author(s) -
Himanshu Jain,
Natasha Sharygina,
Daniel Kroening,
Edmund Clarke
Publication year - 2005
Language(s) - English
Resource type - Reports
DOI - 10.21236/ada470547
Subject(s) - predicate abstraction , computer science , programming language , predicate (mathematical logic) , verilog , abstraction , embedded system , model checking , philosophy , epistemology , field programmable gate array
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