High Level Synthesis in ASP

: The purpose of the Advanced Silicon complier in Prolog project is to synthesize high-quality VLSI layouts from high-level specifications. The ASP system consists of two major components. The low-level part produces masks from functional blocks containing logic equations. The high-level part generates the input to the low-level part from instruction-set level specifications written in Prolog. This document describes the high-level part. Section one presents its general organization. Section two describes its first stage, register allocation. Section three describes its second stage, operation scheduling and finite state machine construction. Section four defines the structural description mechanism that is the interface between the high-level part and the low-level part.