Implementation of VLSI interconnect design

One of the key problems in VLSI interconnect design is the topology construction of signal nets with the minimum cost. The Steiner tree problem is to find the tree structure which connects all pins of the signal net such that the wire length (i.e., cost) can be minimized. If all edges of the tree are restricted to the horizontal and vertical directions as are the case in VLSI design, the problem is called rectilinear Steiner tree (RST).The problem of optimizing interconnections between microelectronic devices is an evolving area under VLSI architectures. Steiner tree is a fundamental problem in the automatic inter-connects optimization for VLSI design. Existing methodologies using a Steiner tree approach are not optimal in terms of path length.