EOT sub-nanométrico y degradación de la movilidad: ¿hacia un límite físico con las técnicas de fabricación modernas?

In this article we investigate the major problem of the micro/nano-electronic: How to reduce the Equivalent Oxide Thickness (EOT) in the sub-nanometric range and improving the MOSFET performance? To reduce the EOT it is necessary that the semiconductor industry introduce the high-K material as the Hafnium (Hf) in the dielectric layer. However the Hf produces a reduction of the mobility and therefore a reduction of the MOSFET speed. We explain through a simple semi-empirical model this mobility degradation in order to familiarize the reader with the concept of mobility for the high-K MOSFET. Afterward we focus on two optimized processing methods for the EOT reduction yielding the best gate stack quality. These processing methods are the Fully-Silicide (FuSi) gate with HfSiON dielectric and the Metal Gate with HfO 2 which are both “gate first” based integration scheme. The important results we found is that first we can obtain a sub-1nm EOT in the both cases although it was thought impossible to make it with high thermal budget process such as the FuSi method. Second, the mobility degradation is very similar in the both case in spite of the very different chemistries we use to form the gate stack. We conclude that the modern deposition technique does not allow controlling the dielectric quality as of 0.8 nm and we suggest using the “gate last” based integration scheme to improve further the gate stack quality.