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Process Development For An Undergraduate Microchip Fabrication Facility
Author(s) -
David Gray,
Christopher Timmons,
R. W. Hendricks
Publication year - 2020
Publication title -
papers on engineering education repository (american society for engineering education)
Language(s) - English
Resource type - Conference proceedings
DOI - 10.18260/1-2--9681
Subject(s) - cleanroom , engineering , semiconductor device fabrication , computer science , electrical engineering , wafer , nanotechnology , materials science
We have built a microchip fabrication facility for teaching the elements of semiconductor processing to a multidisciplinary group of approximately 500 students per year from all areas of engineering, science, and even the humanities. In order to meet our pedagogical objectives of introducing microchip fabrication to introductory students, we have developed a four-mask, ninestep nMOS process using 100 μm rules for use with 4-inch wafers that can be completed by students working in teams of four in six two-hour laboratory periods. Our masksets and the processes used were developed in less than a year, primarily by senior level students in materials, chemical, and electrical engineering.

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