Interdisciplinary Research On Modeling And Scheduling Of Semiconductor Manufacturing Operations

This paper will describe the ongoing interdisciplinary research work of a group of faculty and students working within the Systems Science and Engineering Research Center at Arizona State University (SSERC) in collaboration with INTEL and Motorola. One of the strongest driving forces in the economy of most developed countries is manufacturing. In the United States, one of the most important components of this driving force is the manufacturing of semiconductors in fabrication facilities (FAB). Not surprisingly, tremendous efforts have been expended to reduce the art of semiconductor manufacturing to a science. While the improvements in scale and yield of semiconductor manufacturing has been spectacular and are well known, the improvement in operational methods of process flow and process scheduling have not been as impressive. The most obvious reason for this is the inherent physical/chemical complexity of these processes. Semiconductor manufacturing processes are hundreds of steps long, and factories typically operate multiple processes with each one running many product devices to serve a dynamic marketplace. Process flows are re-entrant and the work in process can be subject to rework. Finite equipment and human resources exhibit a wide range of variability of availability and performance. There are batching or set-up considerations on machines that process by wafer, by lot, or by batch. One practical consequence of all of this complexity is that decisions must be made on very different time-scales. The smallest time-scale being every few minutes during floor operations, usually about resource allocation which step/lot combination to run next, which down machine to repair next, and so on. The medium time-scale of every few days or weeks, responding to market changes. To the largest time-scale of every few months concerning process changes, design improvements, etc. The integration of all of these operational decisions defines the performance of the factory. The key difficulty in making these decisions lies in the intricacy by which they affect the longand short-term factory performance, as well as each other. P ge 591.1 Given the economics of FAB performance, these decisions should be based on sound systems models built on fundamental principals. Unfortunately, these important decisions are currently based on a little local data and rough rules of thumb. The main goals of this research project were: • To investigate novel applications and employ proven tools from the theory of dynamical systems and from control theory to the factory-wide resource scheduling (decision) problem and product release generation in semiconductor manufacturing, and • To develop a model for university-industry dialog in the semiconductor manufacturing area by having industry personnel and interdisciplinary faculty and students working as active participants in the research. The Systems Science and Engineering Research Center SSERC is made up of faculty and students from across many departments and three colleges, College of Engineering and Applied Sciences, College of Liberal Arts and Sciences and the College of Technology and Applied Sciences. The objective of the Center is to foster interdisciplinary research work for faculty and students. The faculty meets at least once per week in a scheduled seminar series where individuals and groups present their latest research. An outside speaker is brought in from either industry or another university several times per semester. The Center also sponsors a 1 to 2 day mini-conference per academic year on topics of specific interest to its members. This has been an excellent model to introduce faculty and students to new ideas for interdisciplinary collaboration. The small group of faculty listed here is an example of this collaboration. Each member brings his/her own expertise and when integrated makes the total more than just the sum of the individuals. This interdisciplinary research encompasses hierarchical mathematical and stochastic simulation modeling for semiconductor manufacturing, from the release of raw wafers at the start through the completion and shipment of the devices. The implementation of “optimal scheduling policies” has recently been recognized as an important and challenging problem in the Semiconductor Industry. The competitive operation of modern fabrication processes requires the development of precise rules for allocating the available resources within the FAB so as to optimize the production performance. Although simply stated, such an objective is elusive, primarily due to the size and complexity of modern FABs. The determination of an optimal scheduling policy remains highly nontrivial, involving the solution of a constrained optimization problem with respect to often-conflicting objectives while any admissible policy must possess certain robustness properties in the presence of uncertainty. This research has developed hierarchical simulation modeling software tools that can be used to manage variabilities arising on the FAB floor. These tools will enable managers and operators to avoid work in progress (WIP) build-ups caused by these variabilities. We investigated the integration of several levels of FAB flow product-release and resourcescheduling algorithms integrated with machine process controllers, including predictive controllers in real time (see Figure 1.) with the aid of discrete event simulation. Information Systems Management Intelligent information systems are at the heart of control, processing and optimization of P ge 591.2 semiconductor manufacturing. Our goals for the information support systems integrated with the FAB Manufacturing Execution System (MES) such as PROMIS or WorkStream and Master Database system such SAP or Oracle include provisions for a knowledge-based, multilevel integrated architecture for information flow/processing across all stages of manufacturing from oxide growth chamber simulations through controller and supervisory levels to the enterprise level. Specifically, in the context of semiconductor manufacturing, data analysis and data mining are the basis for quality control assurance, prediction of time to failure, raw material needs, inventory control, executive report generation, etc. In the context of our multi-level information system architecture, data analysis and filtering must take place at all levels. Basically, raw data is modeled into a summative form, and then passed on for use at another level. As information travels up the hierarchy, more refined numbers and semantics are included. The research involved the development of effective simulation models of existing FABs. Present plans are to extend beyond the simulation and include effective interaction with the FABs relational databases (e.g., Motorola’s PROMIS and Intel’s WorkStream). In particular, bidirectional interfaces for all controllers, schedulers, and release generators are being investigated (Figure 1.). There are four levels in the hierarchy of a FAB integrated simulation model. The lowest level (level 1) comprises machine process controllers; next (level 2) predictive controllers; third (level 3) resource schedulers, and finally (level 4) the product release generator. The long-range objective of this research is to assist FAB Managers in maintaining a stable FAB with maximum utilization of resources and with minimum inventory in an acceptable time frame. Our research was based on past and existing multidisciplinary ASU/Intel team(s) and ASU/Motorola team(s) organized through the SSERC working on operational methods for semiconductor manufacturing. The ASU/Intel team(s) have been working on an Intel provided abstract problem of the FAB process and the ASU/Motorola team(s) have been working in several FABs solving multiple scale problems from the atomistic scale of Chemical Vapor Deposition (CVD) to machine level controllers in diffusion and to predictive controllers for Reactive Ion Etch (RIE) process to resource scheduling and product release generators of actual FABs. A specific problem motivated by these predictive maintenance controllers is to design scheduling and release policies that maintain the highest possible performance in the presence of regular maintenance operations or, in general, predictable equipment failures. It is clear that for this to be possible, the scheduling algorithm should exchange information with the low-level controllers and in turn with the release policy generator. In this respect, our goal was to investigate the type of information that needs to be communicated. For example, based on our recent work on uncertainty characterization in system identification, the "in-spec" operation of the real-time controllers can be described with relatively simple and computable measures. While such procedures can help in predicting potential equipment failures, the use of this information by the scheduling and release policies remains unclear. During our recent work we P ge 591.3 Machine Control Predictive Control Resource Scheduler Production Release Generator Distributed Processing Bay 1 Bay 2 Bay n CORBA IA64 IA64 IA64 Workstations Parallel Processing SAP