A Vhdl Course For Electronics Engineering Technology

Hardware Description Languages, VHDL and Verilog HDL, are being used extensively in industry to describe digital systems from very abstract levels down to gate levels and are in greater and greater use every day. Students who are trained in either of these languages have an advantage in the job market. The Electronics and Computer Engineering Technology Department at Arizona State University has offered a course in VHDL to both undergraduate and graduate students for the past three years. Students learn the basics of the language in addition to many advanced techniques such as generate statements, guarded signals and block statements. An attractive serendipity of a course in VHDL is that students are forced to learn (or re-learn) more accurately how hardware elements operate because they can cannot model the hardware operation unless they understand it. Students learn to describe hardware operations using several VHDL modeling techniques such as behavioral and structural. The techniques of VHDL are re-enforced through a series of mini-projects and a major final project in which students learn to apply their VHDL knowledge on a commercial grade VHDL simulator. Another benefit that this course has engendered is that several of the graduate students have used their knowledge of the language to incorporate it as either a major or supplemental portion of their masters' projects.