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CMOS analog integrated circuit (IC) design is a technology-dependent process. Analog design follows a process for which the transistor sizing necessary to achieve performance goals is defined by a series of simulation tests. The classroom instruction usually walks through a sequence of exercises on the ways in which characteristics of standard subcircuits are defined by the technology and then these subcircuits are linked together in an integrated cell design, usually that of the 8-transistor operational transconductance amplifier (OTA). The design algorithm for the OTA requires that a set of related circuit configurations be evaluated in order to develop the complete design, with each configuration related to a different performance criterion. The process is necessary and follows a design algorithm, but is not particularly efficient. This paper identifies a technique that reduces much of the extra design overhead by framing the OTA as a single test schematic that is probed and reconfigured by means of a simulation version of a switch matrix. The switch matrix (1) links a set of independent sources and loads to the circuit under test and (2) reconfigures the test topology of the circuit. The design process can be framed as a (user-directed) simulation algorithm. The new technique is of value to both the instruction process and the circuit designer since it is simple and direct. Given the simplicity it is also possible to compare effects of different technologies, usually by the collateral use of a spreadsheet utility and its graph capabilities. The improved environment therefore also serves as an empirical cross-coupling of device theory and circuit design. The student version of Cadence/ORCAD/pSPICE is the principal simulation design utility, with the Excel platform as a complementary utility.

Use Of A Simulation Switch Matrix For Efficient Design Of Cmos Analog Integrated Circuits