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Based on industry trends and advances in silicon manufacturing technology in recent years, it is becoming apparent that future electrical and computer engineers will most likely implement their digital designs using programmable logic devices such as CPLDs and FPGAs, rather than discreet IC components. They may also encounter electronic systems built on such devices in their engineering practice. Therefore, it has become necessary to incorporate related design techniques into courses even at the undergraduate level. This paper discusses the introduction of and teaching of such courses to undergraduates majoring in the Electrical Engineering Technology program at the University of Pittsburgh at Johnstown (UPJ). The paper also describes several considerations taken into account during the adaptation of Hardware Description Languages (HDL) and automation based digital design flow to the UPJ curriculum. The demographics of UPJ’s student population and their immediate careers suggest that most graduates do not pursue graduate studies in computer engineering, nor do they seek employment related to design and manufacture of integrated circuit components. As a result, a detailed in depth study of modern digital design methodologies is not a necessity. The paper explains the course topics and the related laboratory assignments of the core digital electronics course for UPJ undergraduates. The results from a student survey taken at the end of the course to gauge the effectiveness of HDL and associated tools in learning digital electronics are also discussed. The paper elaborates on advantages and disadvantages of using HDL based circuit design in the undergraduate engineering technology curriculum as seen by students. Section I: Introduction: In the not too distant past, student assignments in digital design courses consisted primarily of paper designs, or at best such as in senior design projects they were a large morass of SSI and MSI (Small and Medium Scale Integration) silicon devices plugged on to circuit boards or wiring boards. More time was spent on debugging the connections and wirings than on actual design or in determining functionalities of the system. Even after HDLs such as VHDL have become standards and widely being used in industry, undergraduate academic curriculums in Electrical and Computer engineering were very slow to adopt them [1] because of the cost of the hardware and associated Computer Aided Design (CAD) tools required for digital designs. Even those college level courses that utilized HDL, the designs were limited to use them only for design and simulation stages, and not for hardware implementations. This scenario started to change gradually with the advent of cheaper computers, inexpensive Programmable Logic Devices (PLDs), and the associated development environments. Although the availability and cost of using a programmable logic design methodology was initially prohibitive for most academic environments, this is no longer the case. The P ge 13732.2 flexibility of PLDs and the availability of inexpensive CAD tools with huge academic discounts from the industry that support these devices make them ideal for a wide range of digital design courses. Developing designs in hardware languages and associated methodologies teach students the skills to implement large and complex circuits using high level abstraction and adds marketable tools to the student’s skill set. Prior to adaptation of HDL based flows, digital designs were described on paper or on graphical schematics CAD tools by connecting the vendor supplied icons of building blocks named cells. It was of such low level and so tedious that the productivity was very low. Compared to schematic-based design, HDLs provide designers with the following advantages [3]: • Designs can be transcribed at various levels of abstraction. Designers can write their register transfer language (RTL) descriptions without choosing a specific fabrication technology. Logic synthesis tools can automatically convert the design to any fabrication technology. • Describing designs in HDLs allows functional verification of the design early in the design cycle. Because designers work at the RTL level, they can optimize and modify the RTL description until it meets the desired functionality. Most design bugs are eliminated at this point. This significantly decreases design cycle time. • Designing with HDLs is analogous to computer programming. A textual description with comments is an easier way to develop and debug circuits. Gatelevel schematics can be very cumbersome and functionally opaque for complex digital designs. Based on industry trends it is becoming apparent that future electrical and computer technology engineers will most likely implement their digital designs using programmable logic devices such as CPLDs and FPGAs, rather than discreet IC components, while only a very minute fraction of digital designs would be made in either Application Specific Integrated Circuit (ASIC) technology or in discrete logic components such as gates and flipflops. From the papers published in recent years in various venues [4~8] it is apparent that the academic departments are adding new courses or content to teach HDL based design flows at some level to undergraduate EET students. Therefore, to help the graduates to be competent and competitive in their major disciplines, UPJ EET majors are exposed to the HDL based digital design techniques at the undergraduate level. There were several key considerations taken into account during the adaptation of Hardware Description Languages (HDL) and automation based digital design flow to the UPJ curriculum. The demographics of UPJ’s student population and their immediate careers suggest that most graduates do not pursue graduate studies in computer engineering, nor do they seek employment related to design and manufacture of Integrated Circuit components. The primary objective of EET program at UPJ has been to provide a broad skill sets to graduates to work in various local and regional industries including the defense sector, and therefore the EET curriculum does not provide formally declared specialization areas. The P ge 13732.3 core curriculum schedule accommodates only one digital design course namely EET 1161 “Digital Electronics” in the junior year. In the senior year an elective is offered that looks deeper in to system level design using software/hardware co design, design verification, testing, design for test, and advanced design topics. The EET 1161 course is accompanied by its associated laboratory course, EET 1061. The academic calendar of UPJ provides 15 weeks for the courses and about three hours contact time a week for each course. Section II of the paper describes the Course objectives and Content along the description of selected sections of the typical HDL based design flow to suit the UPJ EET curriculum; Section III elaborates on laboratory experiments and project assignments while Section IV ponders upon a survey done on students in the course at the end of the semester. Section V states concluding remarks with the future treads. Section II : Course objectives and Content The objective of the course and the lab is to provide students with a skill set so they would be able to analyze, develop, design and implement a reasonable large and complex digital logic circuit using either discrete components or a PLD. Table 1 shows the course topics and the relevant lab topics for the course. The theme of the course may be viewed as consisting of the following four sections: Section A: Digital logic foundations such as number systems and arithmetic, Boolean algebra and expressions; Section B: Combinational logic design; Section C: Sequential logic design; Section D: Design techniques using hierarchy and commonly used circuit blocks. The course topics are not grouped in to those four sections; rather the course is organized into topics in the sequential order as shown in TABLE 1 to provide a progressive learning flow. Lecture Topics Lab Topics 1 Information representation in Digital Systems: decimal, binary, and hexadecimal systems; Lab 1: introduction of logic families, digital trainers, threshold voltages, etc. 2 Boolean Algebra and function minimizations using Karnaugh Maps, etc Lab 2~3: Boolean functions and Boolean algebraic manipulations, minimizations 3 Combinational Logic elements: Basic and complex logic gates; high impedance output gates; partitioning for single and multi level optimizations. Lab 4~5: Combinational logic design, design partitioning, Boolean manipulations 4 Combinational Logic Design and Functions: Top-down and bottom-up design and hierarchy; Design automation and Lab 6: Combinational logic design with gate level Verilog HDL, testbench creation using P ge 13732.4 implementation methods; Role of Hardware Description Languages in design automation; Technology libraries; propagation delays; simulation and verification of circuits; decoders; multiplexors; encoders; Logic circuit synthesis using pre-designed function blocks. Verilog procedural blocks, Verilog models of standard hardware components to emulate hardware for functionally verifying the designed circuit. Lab 7: Parameterized designs, hierarchical designs, Verilog testbench developments, and a case for non-exhaustive testing 5 Arithmetic Circuits: Iterative combinational circuits; adders; subtracters; arithmetic overflow; multiplication by constants; increments and decrements. Lab 8: Sequential adder using iterative adder blocks implemented in hardware LSI/MSI silicon parts. 6 Sequential Circuit Design: sequential logic elements and timing diagrams; sequential circuit analysis and design; state diagrams; state assignments; one-hot encoding; Different abstract levels of Verilog HDL language, simulation and verification of sequential designs. Lab 9: Design of a finite state machine in HDL and verification by simulation with a testbench. Lab 10:

Incorporating Hdl Based Design Flow In Eet Curriculum