Verification Of Hardware Description Language Designs
Author(s) -
Joanne DeGroat
Publication year - 2020
Publication title -
2006 annual conference and exposition proceedings
Language(s) - Uncategorized
Resource type - Conference proceedings
DOI - 10.18260/1-2--308
Subject(s) - computer science , hardware description language , state (computer science) , computer hardware , chip , computer architecture , structuring , field (mathematics) , integrated circuit , logic synthesis , point (geometry) , digital electronics , register transfer level , embedded system , logic gate , programming language , electronic circuit , field programmable gate array , engineering , electrical engineering , operating system , telecommunications , geometry , mathematics , finance , algorithm , pure mathematics , economics
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