Pedagogic Considerations For Teaching Digital System Design Using Vhdl

Over the last four years, system-level design methodologies have been taught in an “Advanced Digital Design” course at Bucknell University. VHDL is used to define the functions and structures of a digital system. The writing of a hardware description is very different from writing a program for software applications. Effective teaching of a hardware description language such as VHDL is a challenging task. To improve the effectiveness of teaching digital system design using VHDL, numerous pedagogic considerations have been taken into account. In this paper major pedagogic considerations including course organization and materials are described. Student feedback was collected and analyzed; the effectiveness of each course module is reviewed. Common mistakes and general guidelines of writing VHDL descriptions for synthesis are also presented.