A Cad Based Design Course Using State Of The Art System Level Language

Data Types Arbitrary Precision Integers Fixed Point Numbers C++ Built-In Types (int, char, double, etc.) C++ User-Defined Types Logic Data Types Logic Type (01XZ) Logic Vectors Bits and Bit Vectors Figure 1. SystemC architecture. P ge 910.2 Proceedings of the 2004 American Society for Engineering Education Annual Conference & Exposition Copyright © 2004, American Society for Engineering Education The initial introduction in the course involved the history of SystemC, role of SystemC and the infrastructure requirement and setup for running and simulating SystemC design. Important data types supported in SystemC for expressing hardware design is discussed next. The data types discussed included sc_bit, sc_logic, bit-vector, logic vector, sc_int<>, sc_uint<> and sc_bigint<>. Suitable examples were provided for better understanding of the salient properties of each data type and when to choose one over the other. We also discussed differences between Verilog a hardware description language and SystemC as appropriate. During the introduction of the core language concepts we used many design examples. Each of the design examples was carefully chosen so as to explain the SystemC core concepts clearly. The design examples varied in complexity starting with the design of a simple 1-bit half adder to more complex designs involving the design of state-machines. All the SystemC code for different designs developed followed a similar pattern as shown in Figure 2. The lowest levels (level 2 and higher) involved the modules providing the functionality of the target design. This could be made up of more layers depending on the complexity and modularity required in the design. Above the module description layer is the “TOP” module (level 1) in which we provide the test bench code for testing the design developed. Finally the sc_main ( ) (level 0) function is from where the simulation begins. Due to the inherent hierarchy followed in this standard pattern it made it easy to develop design models, understand, extend and reuse. Figure 2. SystemC design module pattern followed. Reusability is ensured by suitably using the modules developed at lower levels in subsequent higher levels. Reusability in SystemC is also supported by suitable parameterization of the design module. Reusability is showcased with the help of simple example wherein we initially developed a simple 1-bit half adder and use this to develop a 4-bit adder. The example is discussed in more detail here. Figure 3 provides the diagrammatic representation of the 1-bit adder module. Two input ports A and B each of 1-bit size are provided. SUM and Carry are the output ports each of 1 bit size. sc_main()