Interfacing A Graphics Lcd Display To A Dsp Via A Micro Controller Simple Distributed Processing Used To Enhance The Integration Of Dsp And Micro Controller Courses In An Eet Program

This paper describes a hardware arrangement that allows data transfer between the 16-bit fixed point ADSP2181 digital signal processor and a Seiko G1216 graphical LCD via an 8-bit 80C552 micro-controller. In this application, the LCD is used to display the results of a 128-point DFT implemented on the ADSP2181 operating at a sampling frequency of 22.05kHz. The interface, however, provides a more broadly useful mechanism to connect slow external devices to the DSP processor without incurring the wait states that are necessary when interfacing directly to the DSP memory spaces and to offload the processing associated with data manipulation and handshaking with these devices. It also provides a link connecting content of the two required microprocessor courses in the EET undergraduate program. Introduction The sequence of required microprocessor based courses in the EET program at Purdue University consists of an introductory sophomore level course based on the 80C552 micro-controller and an introductory DSP course at junior/senior level using the ADSP2181 digital signal processor. The DSP course includes the operation and programming of a fixed-point processor and then moves on to cover the theory and implementation of common DSP applications such as filtering, audio effects and the DFT/FFT. Because of the hardware emphasis in the course, interfacing to I/O devices has been included, permitting some external interaction to take place with the DSP algorithms. Directly interfacing such devices to the processor memory spaces reduces algorithm speed because wait states are needed in any transactions with these slower I/O devices. One alternative approach is to use serial data transfer through the processor’s serial ports and perform all the necessary scaling in the DSP. Another is to use an external controller to handle the acquisition and scaling of data and the appropriate handshaking for slower I/O devices along with relaying data to and from the DSP processor via direct memory access. Simple circuitry to implement the data transfer and handshaking has been developed and is now included in selected laboratory exercises. This way one can extend the interfacing options in the course, take advantage of a wider range of I/O devices such as push buttons, LCD displays, multi-channel ADCs etc. and provide a direct link to earlier micro-processor courses. Student projects can also take advantage of this technique. Microprocessor Hardware The DSP course uses the ADSP-2181 based EZ-Kit Lite, an inexpensive yet versatile development system from Analog Devices. Incorporated onto the EZ_KIT Lite is a 16-bit fixed point, 30ns ADSP-2181 processor with 16k words of internal data memory, 16k words of P ge 730.1 Proceedings of the 2002 American Society for Engineering Annual Conference & Exposition Copyright ” 2002, American Society for Engineering Education program memory and several additional off-chip memory spaces. In addition, there is an AD1847 stereo audio CODEC with programmable sampling rate. Access is provided to all external data, address and control bus lines through expansion connectors on the board. Additional analog peripherals can be connected to the processor through the 2k word 16-bit I/O memory space but would require individual glue logic circuitry to decode bus signals along with wait state insertions to obtain reliable data exchange with slow I/O devices. In contrast, the introductory microprocessor course uses the 80C552 micro-controller along with a variety of I/O devices such as push buttons, potentiometers, LEDs, and LCD displays. All devices connect easily to the various ports on the 80C552 and students have a semester’s experience of working with the system before taking the DSP class. It was in an effort to take advantage of both the 80C552 hardware and the students’ experience and thus provide some continuity between the two courses that the interface between the two systems was developed. The ADSP-2181 IDMA Port The ADSP-2181 provides several means to interface with peripheral processors and devices. In addition to the interface buses used to access the various memory spaces, it contains an Internal Direct Memory Access (IDMA) port. The port supports boot loading and run-time access to the program memory (PM) and data memory (DM) spaces within the ADSP-2181 but does not permit access to internal memory mapped control registers. Control of the IDMA port is achieved through an internal register mapped into DM(0x3FE0) accessible to both the ADSP-2181and the host device (80C552). In this application, only the 80C552 host accesses this register. Data transfer through the IDMA port takes place via the 16bit IDMA port address/data bus and is controlled using the handshaking signals listed in table 1 below. Table 1 IDMA Handshaking Signals Pin Name(s) Active State Input/Outpt Function IRD Low Input IDMA Port Read Strobe IWR Low Input IDMA Port Write Strobe IAL High Input IDMA Port Address Latch Enable IS Low Input IDMA Port Select IAD15-0 Input/Output IDMA Port Address/Data Bus IACK Low Output IDMA Port Access Ready Acknowledge Data transfer is initiated by writing, to the IDMA control register at DM(0x3FE0), a 16-bit word which defines the memory space to be accessed, PM or DM, and a 14-bit starting address. In the next IDMA bus cycle, data is either written to or read from the specified address in the ADSP2181 memory, depending on the whether the port write (IWR) or port read (IRD) strobe lines respectively, are asserted. Following the memory access the address in the IDMA control register is automatically incremented thus avoiding additional address latch cycles when accessing contiguous memory locations. In all IDMA transfers, the port select (IS) must also be asserted. The 80C552 to ADSP-2181 IDMA Interface The IDMA port on the ADSP-2181 is specifically designed for a seamless interface to another 16bit device whereas the 80C552 micro-controller is an 8-bit device. In order to transfer 16-bit data P ge 730.2 Proceedings of the 2002 American Society for Engineering Annual Conference & Exposition Copyright ” 2002, American Society for Engineering Education via the IDMA port, two pairs of 8-bit tri-state latches are used to create two bi-directional ports to temporary hold the upper and lower bytes of data during transfers and also to provide isolation and thereby reduce noise transfer from the 80C552 system to the ADSP2181. A block diagram of the interface is shown below in figure 1. Two complete cycles of the 80C552 are needed for each cycle of the IDMA port. The operation when writing to the ADSP2181 data memory or the IDMA control register is as follows. During the first cycle, the LS byte of the address to be written to the IDMA control register is written to latch C. During the second cycle the MS byte is written to latch A and then the output enable pins of latches A and C are asserted along with the IS control line. Either the IWR or the IAL control lines are also asserted depending on whether data or an address is being written to the IDMA port. Performing the transfers in this order supplies the IDMA port with the complete 16-bit value at one time. When conducting an IDMA read cycle to transfer data to the 80C552, the process described above is reversed. During the first 80C552 external bus cycle, the IS and IRD control lines of the IDMA port are asserted and the MS byte of the data is written to latch B. The output enable for latch B is asserted so that the 80C552 can read the MS bits and the 8 LS bits from the IDMA are latched into latch D. For the second 80C552 cycle, the output of latch B is disabled and the LS byte of the data is read from latch D. All four tri-state latches and the glue logic for the interface is programmed into an Altera 7182 CPLD to reduce chip count. Figure 1 Block diagram of the 80C552 to ADSP-2181 IDMA port interface 8-bit Latch 8-bit Latch 8-bit Latch 8-bit Latch A