Open AccessA 45nm CMOS, low jitter, all-digital delay locked loop with a circuit to dynamically vary phase to achieve fast lock
Author(s) -
Soumya Shivakumar Begur
Publication year - 2011
Language(s) - English
Resource type - Dissertations/theses
DOI - 10.17760/d20002106
Subject(s) - clock domain crossing , jitter , clock skew , digital clock manager , cpu multiplier , delay locked loop , synchronous circuit , clock gating , computer science , lock (firearm) , cmos , electronic engineering , phase locked loop , clock signal , skew , clock drift , propagation delay , clock synchronization , synchronization (alternating current) , engineering , channel (broadcasting) , telecommunications , mechanical engineering
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