Open AccessA low power CMOS design of an all digital phase locked loop
Author(s) -
Jun Zhao
Publication year - 2011
Language(s) - English
Resource type - Dissertations/theses
DOI - 10.17760/d20001051
Subject(s) - phase locked loop , pll multibit , electronic engineering , direct digital synthesizer , frequency synthesizer , cmos , voltage controlled oscillator , power consumption , digitally controlled oscillator , power (physics) , computer science , time to digital converter , engineering , electrical engineering , phase noise , voltage , variable frequency oscillator , jitter , physics , quantum mechanics , clock signal
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