Open AccessData and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples
Author(s) -
Chang-Hyun Bae,
Changsik Yoo
Publication year - 2014
Publication title -
ieice electronics express
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.178
H-Index - 36
eISSN - 1349-9467
pISSN - 1349-2543
DOI - 10.1587/elex.11.20140274
Subject(s) - jitter , intersymbol interference , enhanced data rates for gsm evolution , cmos , computer science , signal edge , equalizer , sample and hold , data recovery , compensation (psychology) , sample (material) , electronic engineering , channel (broadcasting) , electronic circuit , margin (machine learning) , computer hardware , engineering , electrical engineering , telecommunications , digital signal processing , psychology , chemistry , chromatography , machine learning , psychoanalysis , analog signal
A 3-Gbps decision feedback equalizer (DFE) compensating for data and edge inter-symbol interference (ISI) is presented. A speculative architecture is employed to relieve the timing burden on the feedback signal for the DFE wherein the ISI of edge sample is compensated by speculating the DFE based on two-UI earlier data sample. Thereby, the timing margins of the DFE for data and edge ISI compensation are ensured to be larger than 1.0-UI. The proposed DFE has been implemented in a 0.13-μm CMOS technology together with a clock and data recovery (CDR) circuit. The DFE and CDR circuits occupy 0.28-mm2 active area and the DFE consumes 18-mW from a 1.2-V supply. The RMS jitter of the recovered clock is improved from 15.6-ps to 11.9-ps by the proposed edge ISI compensating DFE.
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