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A 3-Gbps decision feedback equalizer (DFE) compensating for data and edge inter-symbol interference (ISI) is presented. A speculative architecture is employed to relieve the timing burden on the feedback signal for the DFE wherein the ISI of edge sample is compensated by speculating the DFE based on two-UI earlier data sample. Thereby, the timing margins of the DFE for data and edge ISI compensation are ensured to be larger than 1.0-UI. The proposed DFE has been implemented in a 0.13-μm CMOS technology together with a clock and data recovery (CDR) circuit. The DFE and CDR circuits occupy 0.28-mm2 active area and the DFE consumes 18-mW from a 1.2-V supply. The RMS jitter of the recovered clock is improved from 15.6-ps to 11.9-ps by the proposed edge ISI compensating DFE.

Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples