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Efficient Variable Length Block Switching Mechanism
Author(s) -
Jaidhar C.D,
A. V. Reddy
Publication year - 2007
Publication title -
international journal of computers communications and control
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.422
H-Index - 33
eISSN - 1841-9844
pISSN - 1841-9836
DOI - 10.15837/ijccc.2007.3.2359
Subject(s) - crossbar switch , computer science , network packet , computer network , scheduling (production processes) , packet switching , queue , speedup , block (permutation group theory) , transmission delay , parallel computing , telecommunications , mathematics , mathematical optimization , geometry
Most popular and widely used packet switch architecture is the crossbar. Its attractive characteristics are simplicity, non-blocking and support for simultaneous multiple packet transmission across the switch. The special version of crossbar switch is Combined Input Crossbar Queue (CICQ) switch. It overcomes the limitations of un-buffered crossbar by employing buffers at each crosspoint in addition to buffering at each input port. Adoption of Crosspoint Buffer (CB) simplifies the scheduling complexity and adapts the distributed nature of scheduling. As a result, matching operation is not needed. Moreover, it supports variable length packets transmission without segmentation. Native switching of variable length packet transmission results in unfairness. To overcome this unfairness, Fixed Length Block Transfer mechanism has been proposed. It has the following drawbacks: (a) Fragmented packets are reassembled at the Crosspoint Buffer (CB). Hence, minimum buffer requirement at each crosspoint is twice the maximum size of the block. When number of ports are more, existence of such a switch is infeasible, due to the restricted memory available in switch core. (b) Reassembly circuit at each crosspoint adds the cost of the switch. (c) Packet is eligible to transfer from CB to output only when the entire packet arrives at the CB, which increases the latency of the fragmented packet in the switch. To overcome these drawbacks, this paper presents Variable Length Block Transfer mechanism. It does not require internal speedup, segmentation and reassembly circuits. Using simulation it is shown that proposed mechanism is superior to Fixed Length Block Transfer mechanism in terms of delay and throughput.

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