A hardware-in-the-loop simulation environment for real-time systems development and architecture evaluation | Zendy

В.В. Балашов | Zendy; A. G. Bakhmurov | Zendy; M.V. Chistolinov | Zendy; Ruslan Smeliansky | Zendy; D. Yu. Volkanov | Zendy; Nikita V. Youshchenko | Zendy

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A hardware-in-the-loop simulation environment for real-time systems development and architecture evaluation

Author(s) -

В.В. Балашов,

A. G. Bakhmurov,

M.V. Chistolinov,

Ruslan Smeliansky,

D. Yu. Volkanov,

Nikita V. Youshchenko

Publication year - 2010

Publication title -

international journal of critical computer-based systems

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.146

H-Index - 10

eISSN - 1757-8787

pISSN - 1757-8779

DOI - 10.1504/ijccbs.2010.031706

Subject(s) - hardware in the loop simulation , computer science , architecture , embedded system , computer architecture , development environment , loop (graph theory) , hardware architecture , development (topology) , software , operating system , software engineering , art , mathematical analysis , mathematics , combinatorics , visual arts

In this paper, we present a technology for integration of distributed real-time embedded systems (RTES) based on hardware-in-the-loop simulation. The environment to support this technology is described. This environment also enables simulation-based development of RTES software and evaluation of RTES architecture on early stages of RTES development.

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