Simulation Environment for Investigation of Delay-Insensitivity of Data Flow Structure Asynchronous Networks and Systems

Clocking is one of the most signi cant problems of VLSI system design. It is not easy to give a general de nition for delay insensitivity, but it is more di cult to verify it for a given digital system. The simulation method proposed by the authors makes possible to follow the classical bottom-up design method from switch level to register-transfer level. The rst step of the proposed designing process is to de ne a structure consisting of delta-delay DI components in VHDL. The following step of the design process is inserting pulse controlled sample-and-hold type switches into the delta delay architecture. These components are virtual, physically not realised models, and they are referred shortly as TBs (Tansfer Boxes) in the paper. If all gates or cells and their interconnections would be represented by TBs, and all possible sequences including simultaneous activations would be executed, the simulation with positive results can be considered a veri cation of delay insensitivity. The paper presents the developed special VHDL-FLI simulation environment, the design and simulation process, and shows several interesting problems in which the author's method played an important role.