Efficient event processing through reconfigurable hardware for algorithmic trading | Zendy

Mohammad Sadoghi | Zendy; Martin Labrecque | Zendy; Harsh Vikram Singh | Zendy; Warren Shum | Zendy; HansArno Jacobsen | Zendy

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Efficient event processing through reconfigurable hardware for algorithmic trading

Author(s) -

Mohammad Sadoghi,

Martin Labrecque,

Harsh Vikram Singh,

Warren Shum,

HansArno Jacobsen

Publication year - 2010

Publication title -

proceedings of the vldb endowment

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.946

H-Index - 134

ISSN - 2150-8097

DOI - 10.14778/1920841.1921029

Subject(s) - complex event processing , computer science , field programmable gate array , event (particle physics) , reconfigurable computing , latency (audio) , predicate (mathematical logic) , computer architecture , embedded system , programming language , telecommunications , physics , process (computing) , quantum mechanics

In this demo, we present fpga-ToPSS (Toronto Publish/Subscribe System Family), an efficient event processing platform for high-frequency and low-latency algorithmic trading. Our event processing platform is built over reconfigurable hardware---FPGAs---to achieve line-rate processing. Furthermore, our event processing engine supports Boolean expression matching with an expressive predicate language that models complex financial strategies to autonomously buy and sell stocks based on real-time financial data.

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