New Ternary Data Encoding for Delay-Insensitive Asynchronous Design

A conventional B-ternary logic for an asynchronous design has many drawbacks, most notably its incomplete truth table of the basic logic gates. This paper presents a new asynchronous ternary logics based on a new data-encoding scheme. The main aim of this research is to provide the flawless truth table for varying logic gates. The asynchronous circuit employing these logics uses two-rail logic for two data bits. It can reduce the number of wire by half comparing to the dual-rail or 1-of-4 data encoding. Furthermore, the proposed encoding scheme reduces switching by 25% to compare with the conventional Bternary one.