A Dynamic Hardware Generation Mechanism Based on Partial Evaluation

Many algorithms have a very efficient hardware implementation that cannot be captured by a general-purpose processor. The static nature of hardware implementations has previously made them unsuitable in a flexible computer. However, modern dynamically-reprogrammable hardware provides the ability to realise new algorithms in hardware at run-time. However, these devices are typically more limited in terms of speed and computing resource than static hardware. In order to reclaim some of the cost of using reprogrammable hardware, we must look to new design methods for optimising implementations for dynamic hardware. By drawing on ideas from software design, this paper demonstrates how the technique of partial evaluation can be used to systematically, and formally, derive efficient specialisations of hardware implementations optimised for dynamic hardware, and further, how one might feasibly perform such specialisation at run-time with minimal cost.