Open AccessAn Optimization Design Strategy for Arithmetic Logic Unit
Author(s) -
Jitesh R. Shinde,
Shilpa J. Shinde
Publication year - 2019
Publication title -
universal journal of electrical and electronic engineering
Language(s) - English
Resource type - Journals
eISSN - 2332-3299
pISSN - 2332-3280
DOI - 10.13189/ujeee.2019.060101
Subject(s) - adder , arithmetic logic unit , computer science , arithmetic , very large scale integration , combinational logic , computer architecture , simple (philosophy) , high level synthesis , digital electronics , computer engineering , parallel computing , logic gate , theoretical computer science , computer hardware , algorithm , electronic circuit , embedded system , field programmable gate array , mathematics , engineering , electrical engineering , telecommunications , philosophy , epistemology , latency (audio)
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