Open AccessLow Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic
Author(s) -
Alireza Hassanzadeh
Publication year - 2015
Publication title -
journal of electrical and electronic engineering
Language(s) - English
Resource type - Journals
eISSN - 2329-1613
pISSN - 2329-1605
DOI - 10.11648/j.jeee.20150306.11
Subject(s) - adder , carry save adder , computer science , power (physics) , parallel computing , electronic engineering , waveform , logic gate , serial binary adder , cyclic prefix , arithmetic , electrical engineering , algorithm , mathematics , cmos , engineering , physics , telecommunications , radar , quantum mechanics , channel (broadcasting) , orthogonal frequency division multiplexing
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