Reconfigurable Signal Processing and Hardware Architecture for Broadband Wireless Communications | Zendy

YingChang Liang | Zendy; Sayed Naveen | Zendy; Santosh K Pilakkat | Zendy; Ashok Kumar Marath | Zendy

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Reconfigurable Signal Processing and Hardware Architecture for Broadband Wireless Communications

Author(s) -

YingChang Liang,

Sayed Naveen,

Santosh K Pilakkat,

Ashok Kumar Marath

Publication year - 2005

Publication title -

eurasip journal on wireless communications and networking

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.461

H-Index - 64

eISSN - 1687-1499

pISSN - 1687-1472

DOI - 10.1155/wcn.2005.323

Subject(s) - cyclic prefix , computer science , code division multiple access , transceiver , orthogonal frequency division multiplexing , computer hardware , wireless , electronic engineering , channel (broadcasting) , computer network , telecommunications , engineering

This paper proposes a broadband wireless transceiver which can be reconfigured to any type of cyclic-prefix (CP) -based communication systems, including orthogonal frequency-division multiplexing (OFDM), single-carrier cyclic-prefix (SCCP) system, multicarrier (MC) code-division multiple access (MC-CDMA), MC direct-sequence CDMA (MC-DS-CDMA), CP-based CDMA (CP-CDMA), and CP-based direct-sequence CDMA (CP-DS-CDMA). A hardware platform is proposed and the reusable common blocks in such a transceiver are identified. The emphasis is on the equalizer design for mobile receivers. It is found that after block despreading operation, MC-DS-CDMA and CP-DS-CDMA have the same equalization blocks as OFDM and SCCP systems, respectively, therefore hardware and software sharing is possible for these systems. An attempt has also been made to map the functional reconfigurable transceiver onto the proposed hardware platform. The different functional entities which will be required to perform the reconfiguration and realize the transceiver are explained.

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