Design of Three-Dimensional Multiple Slice Turbo Codes

This paper proposes a new approach to designing low-complexity high-speed turbo codes for very low frame error rate applications. The key idea is to adapt and optimize the technique of multiple turbo codes to obtain the required frame error rate combined with a family of turbo codes, called multiple slice turbo codes (MSTCs), which allows high throughput at low hardware complexity. The proposed coding scheme is based on a versatile three-dimensional multiple slice turbo code (3D-MSTC) using duobinary trellises. Simple deterministic interleavers are used for the sake of hardware simplicity. A new heuristic optimization method of the interleavers is described, leading to excellent performance. Moreover, by a novel asymmetric puncturing pattern, we show that convergence can be traded off against minimum distance (i.e., error floor) in order to adapt the performance of the 3D-MSTC to the requirement of the application. Based on this asymmetry of the puncturing pattern, two new adapted iterative decoding structures are proposed. Their performance and associated decoder complexities are compared to an 8-state and a 16-state duobinary 2D-MSTC. For a 4 kb information frame, the 8-state trellis 3D-MSTC proposed achieves a throughput of 100 Mbps for an estimated area of 2.9mm2 in a 0.13µm technology. The simulation results show that the FER is below 10-6 at SNR of 1.45 dB, which represents a gain of more than 0.5 dB over an 8-state 2D-MSTC. The union bound gives an error floor that appears at FER below 10-8. The performance of the proposed 3D-MSTC for low FERs outperforms the performance of a 16-state 2D-MSTC with 20% less complexity.