Design of a 108 Pin VLSI Package With Low Thermal Resistance | Zendy

Kanji Ōtsuka | Zendy; Tamotsu Usami | Zendy

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Design of a 108 Pin VLSI Package With Low Thermal Resistance

Author(s) -

Kanji Ōtsuka,

Tamotsu Usami

Publication year - 1982

Publication title -

active and passive electronic components

Language(s) - English

Resource type - Journals

eISSN - 1026-7034

pISSN - 0882-7516

DOI - 10.1155/apec.10.311

Subject(s) - package design , very large scale integration , thermal resistance , quad flat no leads package , package on package , system in package , integrated circuit packaging , thermal , power (physics) , computer science , integrated circuit , engineering , electrical engineering , electronic engineering , materials science , engineering drawing , chip , nanotechnology , physics , meteorology , wafer dicing , adhesive , layer (electronics) , quantum mechanics , wafer

The design of a 108 pin VLSI package is described. The package has low thermal resistance and can, therefore, dissipate 4 watts of power. The package design is now being used commercially in high-end computers made by Hitachi.

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