FPGA Realization and Lyapunov–Krasovskii Analysis for a Master-Slave Synchronization Scheme Involving Chaotic Systems and Time-Delay Neural Networks | Zendy

Joel Pérez Padron | Zendy; C. Posadas–Castillo | Zendy; José P. Pérez | Zendy; Ernesto Zambrano-Serrano | Zendy; Miguel Ángel Platas-Garza | Zendy

Open Access

FPGA Realization and Lyapunov–Krasovskii Analysis for a Master-Slave Synchronization Scheme Involving Chaotic Systems and Time-Delay Neural Networks

Author(s) -

Joel Pérez Padron,

C. Posadas–Castillo,

José P. Pérez,

Ernesto Zambrano-Serrano,

Miguel Ángel Platas-Garza

Publication year - 2021

Publication title -

mathematical problems in engineering

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.262

H-Index - 62

eISSN - 1026-7077

pISSN - 1024-123X

DOI - 10.1155/2021/2604874

Subject(s) - field programmable gate array , realization (probability) , synchronization (alternating current) , chaotic , control theory (sociology) , scheme (mathematics) , computer science , tracking (education) , artificial neural network , trajectory , stability theory , synchronization of chaos , control (management) , mathematics , embedded system , artificial intelligence , nonlinear system , physics , psychology , mathematical analysis , statistics , pedagogy , astronomy , quantum mechanics , computer network , channel (broadcasting)

In this paper, the trajectory tracking control and the field programmable gate array (FPGA) implementation between a recurrent neural network with time delay and a chaotic system are presented. The tracking error is globally asymptotically stabilized by means of a control law generated from the Lyapunov–Krasovskii and Lur’e theory. The applicability of the approach is illustrated by considering two different chaotic systems: Liu chaotic system and Genesio–Tesi chaotic system. The numerical results have shown the effectiveness of obtained theoretical results. Finally, the theoretical results are implemented on an FPGA, confirming the feasibility of the synchronization scheme and showing that it is hardware realizable.

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