Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits | Zendy

Vikas Saini | Zendy; Shamim Akhter | Zendy; Tanuj Chauhan | Zendy

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Implementation, Test Pattern Generation, and Comparative Analysis of Different Adder Circuits

Author(s) -

Vikas Saini,

Shamim Akhter,

Tanuj Chauhan

Publication year - 2016

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/2016/1260879

Subject(s) - adder , carry save adder , computer science , serial binary adder , carry (investment) , arithmetic , compiler , parallel computing , computer hardware , mathematics , telecommunications , finance , economics , programming language , latency (audio)

Addition usually affects the overall performance of digital systems and an arithmetic function. Adders are most widely used in applications like multipliers, DSP (i.e., FFT, FIR, and IIR). In digital adders, the speed of addition is constrained by the time required to propagate a carry through the adder. Various techniques have been proposed to design fast adders. We have derived architectures for carry-select adder (CSA), Common Boolean Logic (CBL) based adders, ripple carry adder (RCA), and Carry Look-Ahead Adder (CLA) for 8-, 16-, 32-, and 64-bit length. In this work we have done comparative analysis of different types of adders in Synopsis Design Compiler using different standard cell libraries at 32/28 nm. Also, the designs are analyzed for the stuck at faults (s-a-0, s-a-1) using Synopsis TetraMAX

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