A Discrete Event System Approach to Online Testing of Speed Independent Circuits
Author(s) -
Pradeep Kumar Biswal,
Kush Mishra,
Santosh Biswas,
Hemangee K. Kapoor
Publication year - 2015
Publication title -
vlsi design
Language(s) - English
Resource type - Journals
eISSN - 1065-514X
pISSN - 1026-7123
DOI - 10.1155/2015/651785
Subject(s) - semaphore , correctness , asynchronous communication , computer science , testability , event (particle physics) , overhead (engineering) , computer engineering , electronic circuit , asynchronous circuit , fault (geology) , detector , fault coverage , state (computer science) , multiplexer , embedded system , reliability engineering , algorithm , multiplexing , engineering , clock signal , electrical engineering , programming language , computer network , telecommunications , physics , quantum mechanics , seismology , synchronous circuit , geology
With the increase in soft failures in deep submicron ICs, online testing is becoming an integral part of design for testability. Some techniques for online testing of asynchronous circuits are proposed in the literature, which involves development of a checker that verifies the correctness of the protocol. This checker involves Mutex blocks making its area overhead quite high. In this paper, we have adapted the Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems to online testing of speed independent asynchronous circuits. The scheme involves development of a state based model of the circuit, under normal and various stuck-at fault conditions, and finally designing state estimators termed as detectors. The detectors monitor the circuit online and determine whether it is functioning in normal/failure mode. The main advantages are nonintrusiveness and low area overheads compared to similar schemes reported in the literature
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