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Terminal Satisfiability in GSTE
Author(s) -
Yongsheng Xu,
Guowu Yang,
Zhengwei Chang,
Desheng Zheng,
Wensheng Guo
Publication year - 2014
Publication title -
journal of applied mathematics
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.307
H-Index - 43
eISSN - 1687-0042
pISSN - 1110-757X
DOI - 10.1155/2014/725275
Subject(s) - satisfiability , model checking , computer science , arbiter , assertion , algorithm , symbolic trajectory evaluation , formal verification , terminal (telecommunication) , satisfiability modulo theories , boolean satisfiability problem , theoretical computer science , programming language , parallel computing , telecommunications
Generalized symbolic trajectory evaluation (GSTE) is an extension of symbolic trajectory evaluation (STE) and a method of model checking. GSTE specifications are given as assertion graphs. There are four efficient methods to verify whether a circuit model obeys an assertion graph in GSTE, Model Checking Strong Satisfiability (SMC), Model Checking Normal Satisfiability (NMC), Model Checking Fair Satisfiability (FMC), and Model Checking Terminal Satisfiability (TMC). SMC, NMC, and FMC have been proved and applied in industry, but TMC has not. This paper gives a six-tuple definition and presents a new algorithm for TMC. Based on these, we prove that our algorithm is sound and complete. It solves the SMC’s limitation (resulting in false negative) without extending from finite specification to infinite specification. At last, a case of using TMC to verify a realistic hardware circuit round-robin arbiter is achieved. Avoiding verifying the undesired paths which are not related to the specifications, TMC makes it possible to reduce the computational complexity, and the experimental results suggest that the time cost by SMC is 3.14× with TMC in the case

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