Design of Low Power and Efficient Carry Select Adder Using 3-T XOR Gate | Zendy

Gagandeep Singh | Zendy; Chakshu Goel | Zendy

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Design of Low Power and Efficient Carry Select Adder Using 3-T XOR Gate

Author(s) -

Gagandeep Singh,

Chakshu Goel

Publication year - 2014

Publication title -

advances in electronics

Language(s) - English

Resource type - Journals

eISSN - 2356-6663

pISSN - 2314-7881

DOI - 10.1155/2014/564613

Subject(s) - adder , xor gate , power–delay product , serial binary adder , carry save adder , computer science , arithmetic , carry (investment) , 4 bit , power consumption , power (physics) , 16 bit , logic gate , computer hardware , electronic engineering , engineering , mathematics , cmos , telecommunications , algorithm , physics , finance , quantum mechanics , economics , latency (audio)

In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP) as compared to regular CSLA and modified CSLA

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