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Gate-Level Circuit Reliability Analysis: A Survey
Author(s) -
Ran Xiao,
Chunhong Chen
Publication year - 2014
Publication title -
vlsi design
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.123
H-Index - 24
eISSN - 1065-514X
pISSN - 1026-7123
DOI - 10.1155/2014/529392
Subject(s) - reliability (semiconductor) , reliability engineering , computer science , nanoelectronics , circuit design , electronic circuit , electronic engineering , engineering , electrical engineering , embedded system , materials science , power (physics) , physics , quantum mechanics , nanotechnology
Circuit reliability has become a growing concern in today’s nanoelectronics, which motivates strong research interest over the years in reliability analysis and reliability-oriented circuit design. While quite a few approaches for circuit reliability analysis have been reported, there is a lack of comparative studies on their pros and cons in terms of both accuracy and efficiency. This paper provides an overview of some typical methods for reliability analysis with focus on gate-level circuits, large or small, with or without reconvergent fanouts. It is intended to help the readers gain an insight into the reliability issues, and their complexity as well as optional solutions. Understanding the reliability analysis is also a first step towards advanced circuit designs for improved reliability in the future research

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