Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

peer-reviewedComplexity in processor microarchitecture and the related issues of power density, hot spots and wire delay, are seen to be a major\udconcern for design migration into low nanometer technologies of the future.This paper evaluates the hardware cost of an alternative\udto register-file organization, the superscalar stack issue array (SSIA).We believe this is the first such reported study using discrete\udstack elements. Several possible implementations are evaluated, using a 90 nm standard cell library as a reference model, yielding\uddelay data and FO4 metrics.The evaluation, including reference to ASIC layout, RC extraction, and timing simulation, suggests a\ud4-wide issue rate of at least four Giga-ops/sec at 90nm and opportunities for twofold future improvement by using more advanced\uddesign approaches.PUBLISHE