Open AccessPerformance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits
Author(s) -
Shikha Panwar,
Mayuresh Piske,
Aatreya Vivek Madgula
Publication year - 2014
Publication title -
vlsi design
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.123
H-Index - 24
eISSN - 1065-514X
pISSN - 1026-7123
DOI - 10.1155/2014/380362
Subject(s) - nmos logic , cmos , electronic circuit , cadence , power gating , electronic engineering , transistor , propagation delay , computer science , power–delay product , power (physics) , node (physics) , electrical engineering , voltage , engineering , adder , physics , structural engineering , quantum mechanics
This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption
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