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FinFETs: From Devices to Architectures
Author(s) -
Debajit Bhattacharya,
Niraj K. Jha
Publication year - 2014
Publication title -
advances in electronics
Language(s) - English
Resource type - Journals
eISSN - 2356-6663
pISSN - 2314-7881
DOI - 10.1155/2014/365689
Subject(s) - mosfet , scaling , planar , transistor , logic gate , computer science , electronic engineering , electronic circuit , computer architecture , electrical engineering , engineering , voltage , mathematics , geometry , computer graphics (images)
Since Moore’s law driven scaling of planar MOSFETsfaces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owingto the presence of multiple (two/three) gates, FinFETs/TrigateFETs are able to tackle short-channel effects (SCEs) better thanconventional planar MOSFETs at deeply scaled technology nodesand thus enable continued transistor scaling. In this paper, wereview research on FinFETs from the bottommost device levelto the topmost architecture level. We survey different types ofFinFETs, various possible FinFET asymmetries and their impact,and novel logic-level and architecture-level tradeoffs offered byFinFETs. We also review analysis and optimization tools thatare available for characterizing FinFET devices, circuits, andarchitectures

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