Low Power Decoding of LDPC Codes

Wireless sensor networks are used in many diverse application scenarios thatrequire the network designer to trade off different factors. Two such factors of importancein many wireless sensor networks are communication reliability and batterylife. This paper describes an efficient, low complexity, high throughput channeldecoder suited to decoding low-density parity-check (LDPC) codes. LDPCcodes have demonstrated excellent error-correcting ability such that a number ofrecent wireless standards have opted for their inclusion. Hardware realisation ofpractical LDPC decoders is a challenging area especially when power efficient solutionsare needed. Implementation details are given for an LDPC decoding algorithm,termed adaptive threshold bit flipping (ATBF), designed for low complexityand low power operation. The ATBF decoder was implemented in 90 nm CMOS at0.9 V using a standard cell design flow and was shown to operate at 250 MHz achievinga throughput of 252 Gb/s/iteration. The decoder area was 0.72 mm 2 with a powerconsumption of 33.14 mW and a very small energy/decoded bit figure of 1.3 pJ.