A High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder Cell | Zendy

Shima Mehrabi | Zendy; Reza Faghih Mirzaee | Zendy; Keivan Navi | Zendy; Omid Hashemipour | Zendy

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A High-Efficient Multi-Output Mixed Dynamic/Static Single-Bit Adder Cell

Author(s) -

Shima Mehrabi,

Reza Faghih Mirzaee,

Keivan Navi,

Omid Hashemipour

Publication year - 2013

Publication title -

isrn electronics

Language(s) - English

Resource type - Journals

ISSN - 2090-8679

DOI - 10.1155/2013/376869

Subject(s) - adder , multiplexer , computer science , serial binary adder , digital electronics , carry save adder , electronic engineering , logic gate , electronic circuit , multiplexing , computer hardware , arithmetic , algorithm , electrical engineering , cmos , engineering , mathematics , telecommunications

Dynamic logic is a well-known logic style which is widely used in digital electronics. A mixed dynamic/static full adder cell is presented in this paper with the aim of reaching high efficiency. The midoutputs are obtained from a Multi-output dynamic module. Then, a multiplexer generates final outputs in the static part. Several conventional and state-of-the-art dynamic adders are also surveyed and compared in the paper. All circuits are simulated by HSPICE with 32 nm CNFET technology. The proposed design is the fastest dynamic adder cell. In addition, it has approximately 5% higher efficiency in terms of PDP than the second most high-performance cell, which is DDCVS.

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