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This paper presents a discrete time, single loop, third order ΔΣ modulator. The input feed forward technique combined with 5-bit quantizer is adopted to suppress swings of integrators. Harmonic distortions as well as the noise mixture due to the nonlinear amplifier gain are prevented. The design of amplifiers is hence relaxed. To reduce the area and power cost of the 5-bit quantizer, the successive approximation quantizer with only a single comparator instead of traditional flash quantizer is employed. Fabricated in 65 nm CMOS, the modulator achieves 95 dB peak SNDR at 1-V supply with 24 kHz. Thanks to low swing circuit techniques and low threshold voltages of devices, the peak SNDR maintains 90.2 dB under 0.6-V low supply. The total power dissipation is 371 μW at 1-V and drops to only 133 μW at 0.6-V

vlsi design

A 0.6-V to 1-V Audio <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" id="M1"><mml:mrow><mml:mi mathvariant="normal">Δ</mml:mi><mml:mi mathvariant="bold">Σ</mml:mi></mml:mrow></mml:math> Modulator in 65 nm CMOS with 90.2 dB SNDR at 0.6-V

A 0.6-V to 1-V Audio ΔΣ Modulator in 65 nm CMOS with 90.2 dB SNDR at 0.6-V