Open AccessLeakage Power Analysis of Domino XOR Gate
Author(s) -
Amit Kumar Pandey,
R. A. Mishra,
R. K. Nagaria
Publication year - 2013
Publication title -
isrn electronics
Language(s) - English
Resource type - Journals
ISSN - 2090-8679
DOI - 10.1155/2013/271316
Subject(s) - xor gate , domino , leakage power , domino logic , leakage (economics) , transistor , topology (electrical circuits) , or gate , electronic engineering , electronic circuit , voltage , computer science , logic gate , electrical engineering , engineering , and gate , pass transistor logic , chemistry , biochemistry , economics , macroeconomics , catalysis
Two new XOR gates are proposed. First proposed circuits adopt hybrid transistor topology in the pull-down network with all transistors being low threshold voltages. A second proposed circuit adopts hybrid topology with dual threshold voltage transistors. Simulation parameters are measured at 25°C and 110°C. First proposed circuit reduces leakage power consumption up to 50% at 25°C and 58% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 14% as compared to standard N-type domino XOR gate. Similarly, second proposed circuit reduces leakage power consumption up to 73% at 25°C and 90% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 39% as compared to standard N-type domino XOR gate.
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