Verification of Mixed-Signal Systems with Affine Arithmetic Assertions | Zendy

Carna Radojicic | Zendy; Christoph Grimm | Zendy; Florian Schupfer | Zendy; Michael Rathmair | Zendy

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Verification of Mixed-Signal Systems with Affine Arithmetic Assertions

Author(s) -

Carna Radojicic,

Christoph Grimm,

Florian Schupfer,

Michael Rathmair

Publication year - 2013

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/2013/239064

Subject(s) - assertion , computer science , affine arithmetic , range (aeronautics) , signal (programming language) , affine transformation , mixed signal integrated circuit , computer engineering , theoretical computer science , algorithm , formal verification , arithmetic , programming language , mathematics , integrated circuit , engineering , pure mathematics , aerospace engineering , operating system

Embedded systems include an increasing share of analog/mixed-signal components that are tightly interwoven with functionality of digital HW/SW systems. A challenge for verification is that even small deviations in analog components can lead to significant changes in system properties. In this paper we propose the combination of range-based, semisymbolic simulation with assertion checking. We show that this approach combines advantages, but as well some limitations, of multirun simulations with formal techniques. The efficiency of the proposed method is demonstrated by several examples

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