MCML D-Latch Using Triple-Tail Cells: Analysis and Design | Zendy

Kirti Gupta | Zendy; Neeta Pandey | Zendy; Maneesha Gupta | Zendy

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MCML D-Latch Using Triple-Tail Cells: Analysis and Design

Author(s) -

Kirti Gupta,

Neeta Pandey,

Maneesha Gupta

Publication year - 2013

Publication title -

active and passive electronic components

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.144

H-Index - 22

eISSN - 1026-7034

pISSN - 0882-7516

DOI - 10.1155/2013/217674

Subject(s) - spice , cmos , voltage , power (physics) , topology (electrical circuits) , electronic engineering , current mode logic , computer science , power consumption , engineering , electrical engineering , physics , quantum mechanics

A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML D-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18 µm CMOS technology parameters

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