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Effects of Annealing Time on the Performance of OTFT on Glass with ZrO2as Gate Dielectric
Author(s) -
Wing Man Tang,
Michael G. Helander,
Mark Greiner,
ZhengHong Lu,
Wai Tung Ng
Publication year - 2012
Publication title -
active and passive electronic components
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.144
H-Index - 22
eISSN - 1026-7034
pISSN - 0882-7516
DOI - 10.1155/2012/901076
Subject(s) - materials science , thin film transistor , annealing (glass) , dielectric , optoelectronics , subthreshold conduction , gate dielectric , subthreshold slope , threshold voltage , transistor , high κ dielectric , voltage , electrical engineering , composite material , layer (electronics) , engineering
Copper phthalocyanine-based organic thin-film transistors (OTFTs) with zirconium oxide (ZrO2) as gate dielectric have been fabricated on glass substrates. The gate dielectric is annealed in N2 at different durations (5, 15, 40, and 60 min) to investigate the effects of annealing time on the electrical properties of the OTFTs. Experimental results show that the longer the annealing time for the OTFT, the better the performance. Among the devices studied, OTFTs with gate dielectric annealed at 350°C in N2 for 60 min exhibit the best device performance. They have a small threshold voltage of −0.58 V, a low subthreshold slope of 0.8 V/decade, and a low off-state current of 0.73 nA. These characteristics demonstrate that the fabricated device is suitable for low-voltage and low-power operations. When compared with the TFT samples annealed for 5 min, the ones annealed for 60 min have 20% higher mobility and nearly two times smaller the subthreshold slope and off-state current. The extended annealing can effectively reduce the defects in the high-k film and produces a better insulator/organic interface. This results in lower amount of carrier scattering and larger CuPc grains for carrier transport

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