Open AccessOpen SystemC Simulator with Support for Power Gating Design
Author(s) -
George Sobral Silveira,
Alisson V. Brito,
Helder F. de A. Oliveira,
Elmar U. K. Melcher
Publication year - 2012
Publication title -
international journal of reconfigurable computing
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.236
H-Index - 16
eISSN - 1687-7209
pISSN - 1687-7195
DOI - 10.1155/2012/793190
Subject(s) - systemc , computer science , power gating , block (permutation group theory) , power (physics) , embedded system , abstraction , transaction level modeling , functional verification , process (computing) , computer architecture simulator , computer architecture , simulation , formal verification , operating system , programming language , voltage , transistor , physics , geometry , mathematics , quantum mechanics , philosophy , epistemology
Power gating is one of the most efficient power consumption reduction techniques. However, when applied in several different parts of a complex design, functional verification becomes a challenge. Lately, the verification process of this technique has been executed in a Register-Transfer Level (RTL) abstraction, based on the Common Power Format (CPF) and the Unified Power Format (UPF). The purpose of this paper is to present an OSCI SystemC simulator with support to the power gating design. This simulator is an alternative to assist the functional verification accomplishment of systems modeled in RTL. The possibility of controlling the retention and isolation of power gated functional block (PGFB) is presented in this work, turning the simulations more stable and accurate. Two case studies are presented to demonstrate the new features of that simulator
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