Thermal-Aware Test Schedule and TAM Co-Optimization for Three-Dimensional IC
Author(s) -
Chi-Jih Shih,
Chih-Yao Hsu,
Chun-Yi Kuo,
James Li,
Jiann-Chyi Rau,
Krishnendu Chakrabarty
Publication year - 2012
Publication title -
active and passive electronic components
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.144
H-Index - 22
eISSN - 1026-7034
pISSN - 0882-7516
DOI - 10.1155/2012/763572
Subject(s) - schedule , simulated annealing , integrated circuit , mode (computer interface) , computer science , three dimensional integrated circuit , mathematical optimization , reliability engineering , die (integrated circuit) , test (biology) , thermal , algorithm , engineering , mathematics , biology , operating system , paleontology , physics , meteorology
Testing is regarded as one of the most difficult challenges for three-dimensional integrated circuits (3D ICs). In this paper, we want to optimize the cost of TAM (test access mechanism) and the test time for 3D IC. We used both greedy and simulated annealing algorithms to solve this optimization problem. We compare the results of two assumptions: soft-die mode and hard-die mode. The former assumes that the DfT of dies cannot be changed, while the latter assumes that the DfT of dies can be adjusted. The results show that thermal-aware cooptimization is essential to decide the optimal TAM and test schedule. Blindly adding TAM cannot reduce the total test cost due to temperature constraints. Another conclusion is that soft-die mode is more effective than hard-die mode to reduce the total test cost for 3D IC
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