N Point DCT VLSI Architecture for Emerging HEVC Standard | Zendy

Ashfaq Ahmed | Zendy; Muhammad Shahid | Zendy; Ata Ur Rehman | Zendy

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N Point DCT VLSI Architecture for Emerging HEVC Standard

Author(s) -

Ashfaq Ahmed,

Muhammad Shahid,

Ata Ur Rehman

Publication year - 2012

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/2012/752024

Subject(s) - discrete cosine transform , computer science , very large scale integration , codec , block (permutation group theory) , architecture , parallel computing , computation , parallel architecture , computer architecture , overhead (engineering) , computer engineering , computer hardware , embedded system , algorithm , image (mathematics) , artificial intelligence , mathematics , art , visual arts , geometry , operating system

This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4×4 up to 32×32, the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices in order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed architecture sustains real-time processing of 1080P HD video codec running at 150 MHz

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