Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm | Zendy

S. Jayanthy | Zendy; M. C. Bhuvaneswari | Zendy; Keesarapalli Sujitha | Zendy

AI Assistant Blog Pricing

Home ZAIA Blog

Open Access

Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

Author(s) -

S. Jayanthy,

M. C. Bhuvaneswari,

Keesarapalli Sujitha

Publication year - 2012

Publication title -

vlsi design

Language(s) - English

Resource type - Journals

SCImago Journal Rank - 0.123

H-Index - 24

eISSN - 1065-514X

pISSN - 1026-7123

DOI - 10.1155/2012/745861

Subject(s) - automatic test pattern generation , very large scale integration , electronic circuit , benchmark (surveying) , computer science , crosstalk , algorithm , electronic engineering , fan out , fault coverage , fan in , computer engineering , engineering , chip , electrical engineering , telecommunications , geodesy , geography

As design trends move toward nanometer technology, new problems due to noise effects lead to a decrease in reliability and performance of VLSI circuits. Crosstalk is one such noise effect which affects the timing behaviour of circuits. In this paper, an efficient Automatic Test Pattern Generation (ATPG) method based on a modified Fanout Oriented (FAN) to detect crosstalk-induced delay faults in VLSI circuits is presented. Tests are generated for ISCAS_85 and enhanced scan version of ISCAS_89 benchmark circuits. Experimental results demonstrate that the test program gives better fault coverage, less number of backtracks, and hence reduced test generation time for most of the benchmark circuits when compared to modified Path-Oriented Decision Making (PODEM) based ATPG. The number of transitions is also reduced thus reducing the power dissipation of the circuit

The content you want is available to Zendy users.

Already have an account? Click here to sign in.

Having issues? You can contact us here

Accelerating Research