An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing

As the number of cores per discrete integratedcircuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research inthis area has focused on discrete IC devices alone whichmay or may not serve the high-performance computingcommunity which needs to assemble many of these devicesinto very large scale, parallel computing machines. This paperdescribes an integrated on-chip/off-chip network that hasbeen implemented on an all-FPGA computing cluster. Thesystem supports MPI-style point-to-point messages, collectives,and other novel communication. Results include the resourceutilization and performance (in latency and bandwidth)